Memory devices are typically assembled into memory modules that are used in a computer system. These memory modules typically include single in-line memory modules (SIMMs) having memory devices on one side of the memory module, and dual in-line memory modules (DIMMs) having memory devices on both sides of the memory module. The memory devices of a memory module are accessed in groups. Each of the groups are commonly referred to as “ranks,” with single-sided DIMMs typically having one rank of memory devices and double-sided DIMMs having two ranks of memory devices, one rank on either side of the memory module.
Each of the memory devices of a memory module receives a set of signals, which is generated by a memory controller. These signals include command signals for specifying the type of access of a memory device, such as a read or a write, address signals specifying the location in the memory device being accessed, and write data signals corresponding to data that are to be stored in the memory device. The memory device can also transmits to the memory controller read data signals corresponding to data that have been stored in the memory device.
As the operating speed of memory devices continues to increase, timing margins for the various signals related to memory device operation become more critical, particularly for data signals, which are generally transmitted and received at a higher rate than command and address signals. Subtle variations in signal timing and operating conditions can negatively impact memory device performance. Consequently, it is desirable to improve timing margins without sacrificing performance, where possible.
One factor that can adversely affect timing margins is reflection of signals in conductors through which data signals are coupled. Write data signals and read data signals are typically coupled through a data bus that is coupled to several memory devices. As is well known to one skilled in the art, the conductors of the data bus are transmission lines, which have a characteristic impedance. If the impedance of a memory device data bus terminal is not matched to the characteristic impedance of the data bus conductors, write data signals transmitted to the memory device will be partially reflected from the data bus terminals. Similarly, read data signals transmitted to a memory controller will be partially reflected from the data bus terminals of the memory controller if the impedance of the data bus terminals does not match the characteristic impedance of the data bus conductors. These reflected read and write data signals can remain present on the data bus as subsequent data signals are coupled through the data bus, and they can alter in spurious manner the timing of transitions of these subsequent data signals or the amplitude of these subsequent data signals. The result is a reduction in the timing margins of the memory device.
One approach to improving memory device timing margins is the use of on-die termination (“ODT”) circuits for data bus terminals to which data input/output buffers are connected. The ODT circuits provide resistive terminations that are approximately matched to the characteristic impedance of the data bus conductors to reduce reflections and thereby improve timing margins of the memory device.
The ODT circuits used in a conventional memory device are typically disabled when the memory device is not receiving write data, and they are enabled when the memory device is receiving write data. When the ODT circuit is disabled, the impedances of its associated data bus terminals are very high to simulate an “open circuit” condition in which the memory device is not connected to the data bus, under this condition, the data bus terminals do not substantially reflect data signals. A typical ODT circuit 10 is shown in FIG. 1. The ODT circuit 10 includes a series combination of a first termination resistor 12, which is connected to a supply voltage VCC, a PMOS switching transistor 14, an NMOS switching transistor 16 and a second termination resistor 18, which is connected to ground. The data bus terminal DQ is connected between the transistors 14, 16. The transistor 14 is selectively turned ON by an active high enable signal En, and the transistor 16 is turned ON by its complement, which is generated by an inverter 20.
In operation, the ODT circuit 10 is disabled by an inactive low En signal to turn OFF the transistors 14, 16. The DQ terminals are thus “tri-stated” at a high impedance. When the transistors 14, 16 are turned ON by the active high En signal, the resistors 12, 18 essentially form a voltage divider to set the impedance and bias voltage of the DQ terminal to predetermined values. The resistance of the resistors 12, 18 are generally equal to each other so that the DQ terminal has an impedance of one-half the resistance of the resistors 12,18, and it is biased to a voltage of one-half the supply voltage VCC.
The ODT circuit 10 shown in FIG. 1 can markedly reduce the signal reflections from the DQ terminal. However, its performance in this regard is less than optimum because the resistance of the resistors generally cannot be precisely controlled. As is well-known in the art, the resistors 12, 18 are generally fabricated from a polysilicon material. Presently existing semiconductor fabrication techniques do not allow the resistance of polysilicon resistors to be precisely controlled because of process variations. Even if the resistors 12, 18 could be fabricated with the correct resistances, the resistances would change with time as well as other factors such as temperature changes and supply voltage variations. As a result, the DQ terminals of conventional memory devices using the ODT circuit 10 still cause considerable reflections.
One approach that has been used to deal with the inability to fabricate polysilicon resistors with precisely controlled resistances is an ODT circuit 30 as shown in FIG. 2. The ODT circuit 30 uses many of the same components that are used in the ODT circuit 10 of FIG. 1. Therefore, in the interest of brevity, these components have been provided with the same reference numerals, and an explanation of their characteristics and functions will not be repeated. The ODT circuit 30 differs from the ODT circuit 10 shown in FIG. 1 by connecting a plurality of PMOS transistors 34a,b . . . n in parallel with the first termination resistor 12. Similarly, a plurality of NMOS transistors 36a,b . . . n are connected in parallel with the second termination resistor 18. The transistors 34a,b . . . n and 36a,b . . . n are selectively turned ON by signals from a fuse bank 38.
In operation, the termination resistors 12, 18 are intentionally fabricated with resistances that are higher than target resistances. During wafer test, the impedance at the DQ terminal is measured to determine the resistances of the resistors 12, 18. A conventional programming device (not shown) is then used to program a pattern of fuses or anti-fuses in the fuse bank 38 to provide signals that selectively turn ON the transistors 34a,b . . . n, 36a,b . . . n. Turning ON the transistors 34a,b . . . n, 36a,b . . . n lowers the resistance of the parallel combination of the resistor 12 and the transistors 34a,b . . . n and the resistance of the parallel combination of the resistor 18 and the transistors 36a,b . . . n. The degree to which the resistances are lowered depends on the number of transistors 34a,b . . . n, 36a,b . . . n that are turned ON. The number of transistors 34a,b . . . n, 36a,b . . . n that are turned ON corresponds to the number of fuses or anti-fuses programmed by the programmer. The programmer therefore programs the fuse bank 38 based on the DQ impedance measurement to couple the correct number of transistors 34a,b . . . n, 36a,b . . . n in parallel with the resistors 12, 18, respectively, to provide close to the target DQ impedance.
The ODT circuit 30 shown in FIG. 2 provides a substantial improvement in DQ terminal impedance control over the use of the ODT circuit 10 shown in FIG. 1. However, it still suffers from a number of shortcomings, which cause the DQ terminal to significantly reflect signals applied to the DQ terminal. The primary limitation of the ODT circuit 30 results from changes in the resistances of the resistors 12, 18, as well as changes in the ON impedance of the transistors 34a,b . . . n, 36a,b . . . n over time and as a function of temperature and voltage variations. Therefore, even if the ODT circuit 30 can be precisely programmed with the correct DQ termination impedance during fabrication, the DQ termination impedance may not be correct after a memory device containing the ODT circuit 30 has been placed in operation. It is not possible to reprogram the fuse bank 38 to provide the correct DQ termination impedance because the fuse bank 38 must be programmed before the memory device containing the ODT circuit 30 has been packaged. Furthermore, a considerable time can be required during fabrication to test the resistance of the termination resistors 12, 18 and to then program the fuse bank, which can unduly increase the fabrication costs of memory devices containing the ODT circuit 30.
There is therefore a need for an ODT circuit that does not require expensive and time consuming testing and programming during fabrication, that can be fabricated with the correct DQ termination impedance, and that can adapt to changes in the ODT circuit with time as well as temperature, process and supply voltage variations.